Image processing with pixel interpolation

ABSTRACT

The present invention provides an image signal processing apparatus and a method thereof which shifts positions of each detected pixel in image signals generated by performing double-speed conversion, wherein a difference value in pixel signal level between a detected pixel in a current field and a detected pixel at the same position in a field which comes one frame behind the current field is calculated, to specify a first field, a motion vector for a field which comes one frame or two frames behind the current field is detected with respect to the detected pixel in the current field, interpolation pixel data for the detected pixel is calculated based on the detected pixel in the current field and the each pixel in the field which comes one frame or two frames behind the current field, the interpolation pixel data is disposed in the pixel position obtained by shifting the position of the detected pixel in the current field in a direction along the motion vector, in a field subsequent to the first field, and the shift amount is sequentially increased every time the field shifts from the first field to the following fields within a range of a vector quantity of the detected motion vector.

TECHNICAL FIELD

The present invention relates to an image signal processing apparatuswhich shifts the position of each detected pixel of image signalsgenerated by performing double-speed conversion, and a processing methodthereof.

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 2001-380760 filed Dec. 13,2001, the entire contents of which are incorporated herein by reference.

BACKGROUND ART

As a conventional scanning system used for TV broadcasting, an interlacescanning system which scans every other horizontal scanning lines hasbeen widely used. In this interlace scanning system, every frame imageis formed of a field image consisting of odd-numbered scanning lines anda field image consisting of even-numbered scanning lines, to suppressscreen flicker disturbance which causes the entire screen to flicker,thus preventing deterioration of the screen quality.

The interlace scanning system has been adopted as a standard system fortelevision in countries throughout the world. For example, according toPAL (Phase Alternation by Line) system in European televisionbroadcasting, the field frequency is 50 Hz (frame images: 25frame/second, field images: 50 fields/second).

In particular, the PAL system conventionally adopts a double-speed fieldfrequency system in which the field frequency of inputted image signalsis converted to be doubled from 50 Hz to 100 Hz, by performing aninterpolation processing or the like, expecting further suppression ofthe screen flicker disturbance.

FIG. 1 is a block diagram showing a double-speed field conversioncircuit 5 using the double-speed field frequency system. Thedouble-speed field conversion circuit 5 is integrated in a televisionreceiver 6 which has an input terminal 61, a horizontal/verticaldeflection circuit 62, and a CRT 63. This double-speed field conversioncircuit 5 has a double-speed converter 51, and a frame memory 52.

The double-speed converter 51 writes image signals of 50 fields/secondaccording to the PAL system inputted from the input terminal 61 into theframe memory 52. Also, the double-speed converter 51 reads the imagesignals written in the frame memory 52, at a speed twice higher than thewriting speed. Thus, the frequency of the image signals of 50fields/second is converted to a double frequency, so that image signalsof 100 fields/second can be generated.

The double-speed converter 51 outputs the image signals subjected to thedouble conversion to the CRT 63. The CRT 63 displays the inputted imagesignals on the screen. Horizontal and vertical deflection of the imagesignals in the CRT 63 is controlled based on a horizontal/verticalrectangular wave which is generated by the horizontal/verticaldeflection circuit 62 and has a frequency which is twice that of theinputted image signals.

FIGS. 2A and 2B show a relationship between each field and pixelpositions with respect to image signals before and after thedouble-speed conversion. In each figure, the abscissa axis representstime, and the ordinate axis represents the position of each pixel in thevertical direction. The image signals indicated by white circle marks inFIG. 2A are interlace image signals of 50 fields/second before thedouble-speed conversion, and the image signals indicated by black circlemarks in FIG. 2B are interlace image signals of 100 fields/second afterthe double-speed conversion.

In the image signals shown in FIG. 2A, fields f1 and f2 are signalsgenerated from one single unit-frame of a film. Likewise, fields f3 andf4 constitute one single unit-frame. Since these image signals areinterlace image signals, the pixel positions in the vertical directiondiffer between adjacent fields. Therefore, it is impossible to create anew field between every two adjacent fields with the characteristics ofinterlacing maintained.

Hence, as shown in FIG. 2B, two fields f2′ and f1′ are newly generatedbetween the fields f1 and f2. No new fields are generated between thefields f2 and f3 but two new fields f4′ and f3′ are generated betweenthe fields f3 and f4. That is, one unit-frame is formed of four fieldsforming two frames.

In some cases, those newly generated fields f1′, f2′, . . . are obtainedby using a median filter or the like, supposing that each pixel value isan intermediate value among three pixels surrounding each pixel. Thenewly generated fields f1′, f2′, . . . have the same contents as thefields f1, f2, . . . , respectively.

Specifically, the double-speed field conversion circuit 5 provides partsin each of which two new fields are generated and parts in each of whichno new fields are generated, alternately among fields of image signalsbefore the double-speed conversion. The number of screen images per unittime can thus be increased, so that the screen flicker disturbance aspreviously described can be suppressed.

In order to watch a cinema film consisting of still images of 24unit-frames/second on an ordinary TV set, television-to-cinemaconversion (which will be hereinafter referred to as telecineconversion) is carried out to attain interlace television signals. FIGS.3A and 3B show a relationship between each field and an image positionin case where an image moves in the horizontal direction, with respectto the image signals after the telecine conversion. The abscissa axisrepresents the position of the image in the horizontal direction, andthe ordinate axis represents time. In the image signals before thedouble-speed conversion shown in FIG. 3A, the fields f1 and f2 form onesingle unit-frame, so that the image is displayed at the same position.This image moves in the horizontal direction (to the right side) as thefield shifts to the field f3. Since the field f4 forms part of the sameunit-frame as the field f3, the image is displayed at the same positionas in the field f3.

If image signals shown in FIG. 3A after the telecine conversion aresubjected to the double-speed conversion according to the double-speedfield frequency system, as shown in FIG. 3B, an equal image is displayedat an equal position in the fields f1, f2′, f1′, and f2 forming onesingle unit-frame. Similarly, an equal image is displayed at an equalposition in the fields f3, f4′, f3′ and f4 forming one singleunit-frame.

FIG. 4A shows a relationship between each field and an image position incase where an image moves in the horizontal direction, with respect totelevision signals (hereinafter referred to as TV signals) before thedouble-speed conversion. In FIG. 4A, each field f1, f2, f3 . . . formsone independent unit-frame, so that images are displayed at differentpositions. The image moves, as a whole, in the horizontal direction (tothe right side) every time the field shifts from the field f1 to f2, f3.

When image signals of the TV signals shown in FIG. 4A are subjected tothe double-speed conversion according to the double-speed fieldfrequency system, as shown in FIG. 4B, an equal image is displayed at anequal position in the fields f1, f2′ forming one single unit-frame.Similarly, an equal image is displayed at an equal position in thefields f1′ and f2 forming one single unit-frame.

In the image signals subjected to the double-speed conversion after thetelecine conversion, the image is displayed at one equal position fromthe field f1 to the field f2 as shown in FIG. 3B. On the other hand, theimage greatly moves in the horizontal direction when the field shiftsfrom f2 to f3. Similarly, in the image signals obtained by double-speedconverting the TV signals, the image is displayed at one equal positionfrom the field f1 to the field f2′ as shown in FIG. 4B. On the otherhand, the image greatly moves in the horizontal direction when the fieldshifts from f2′ to f1′.

In particular, output image signals form fields regularly at a cycle ofone field per 1/100 second. Therefore, a time band in which an imagemoves is shorter than another time band in which an image stands still.When a program is actually watched by a CRT, motions of images lookdiscontinuous.

Further, in images of wide variations such as a case where each pixelvalue changes as the image moves in the horizontal direction, it isnecessary to efficiently eliminate the discontinuity in image motion.

DISCLOSURE OF THE INVENTION

An object of the present invention is to provide a novel image signalprocessing apparatus and a method thereof capable of solving problemsinvolved by a conventional image signal processing apparatus asdescribed above and a method thereof.

Another object of the present invention is to provide an image signalprocessing apparatus and a method thereof capable of synergisticallyincreasing image quality by smoothening motions while suppressing screenflicker disturbance, with respect to image signals generated byperforming double-speed conversion, even in images of wide variations.

According to an image signal processing apparatus and a method thereofof the present invention, signals consist of unit-frames each formed offields with a first field in the lead and which have been subjected todouble-speed conversion are inputted, the first field is specified onthe basis of calculated difference values in pixel signal levels,interpolation pixel data is calculated for each detected pixel, and theinterpolation pixel data is written into the pixel positions obtained byshifting the positions of the detected pixels in a direction along themotion vector such that shift amount is gradually increased as the fieldshifts from the specified first field to the following fields.

More specifically, an image signal processing apparatus according to thepresent invention inputted with image signal consist of unit-frames eachformed of fields with a first field in the lead and which has beensubjected to double-speed conversion, comprises: a sequence detectionmeans which calculates, a difference value in pixel signal level betweena detected pixel in a current field and a detected pixel at the sameposition in a field which comes one frame behind the current field, withrespect to the inputted image signal, and specifies the first fieldbased on the difference value; a motion vector detection means whichdetects a motion vector for a field which comes one frame or two framesbehind the current field, with respect to the detected pixel in thecurrent field; a data calculation means which calculates interpolationpixel data for the detected pixel based on the pixel data of thedetected pixel in the current field and the pixel data of each pixel inthe field which comes one frame or two frames behind the current field;and an image control means which writes the interpolation pixel datainto the pixel position obtained by shifting the position of thedetected pixel in the current field in a direction along the motionvector, in a field subsequent to the first field, the image controlmeans sequentially increases the amount with which the position of thedetected pixel is shifted every time the field shifts from the firstfield to the following fields within a range of a vector quantity of thedetected motion vector.

More specifically, an image signal processing method according to thepresent invention further comprises the steps of: inputting an imagesignal consist of unit-frames each formed of fields with a first fieldin the lead and which has been subjected to double-speed conversion;calculating, with respect to the inputted image signal, a differencevalue in pixel signal level between a detected pixel in a current fieldand a detected pixel at the same position in a field which comes oneframe behind the current field to specify a first field based on thedifference value; detecting a motion vector for a field which comes oneframe or two frames behind the current field, with respect to thedetected pixel in the current field; calculating interpolation pixeldata for the detected pixel based on the pixel data of the detectedpixel in the current field and the pixel data of each pixel in the fieldwhich comes one frame or two frames behind the current field; andwriting the interpolation pixel data into the pixel position obtained byshifting the position of the detected pixel in the current field in adirection along the motion vector, in a field subsequent to the firstfield. The image control means sequentially increases the amount withwhich the position of the detected pixel is shifted every time the fieldshifts from the first field to the following fields within a range of avector quantity of the detected motion vector.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, advantages and features of the presentinvention will be more apparent from the following description taken inconjunction with the accompanying drawings.

FIG. 1 is a block diagram showing a double-speed field conversioncircuit to which a double-speed field frequency system is applied;

FIGS. 2A and 2B show a relationship between each of fields before andafter the double-speed conversion and pixel positions;

FIGS. 3A and 3B show a relationship between each field and an imageposition in the case where an image moves in the horizontal direction;

FIGS. 4A and 4B show a relationship between each field and an imageposition when an image moves in the horizontal direction in case whereTV signals are inputted;

FIG. 5 is a block circuit diagram showing an image signal processingapparatus to which the present invention is applied;

FIG. 6 is a block circuit diagram showing an image shifter forming partof the image signal processing apparatus;

FIGS. 7A and 7B show a relationship between each of fields before andafter double-speed conversion in a double-speed field conversion circuitand pixel positions;

FIG. 8 shows a relationship between each field and an image position incase where an image moves in the horizontal direction in atelecine-converted image;

FIG. 9 shows a relationship between each field and an image position incase where an image moves in the horizontal direction in an image formedof TV signals;

FIG. 10 is a view for explaining a method of detecting a sequence;

FIGS. 11A and 11B depict one-dimensionally an operation process of theimage shifter;

FIGS. 12A to 12D show a concrete operation example of the image shifterusing pixel values; and

FIG. 13 is a block diagram of the image shifter in which the priority atthe time of writing data is not determined.

BEST MODE FOR CARRYING OUT THE INVENTION

An image signal processing apparatus and a method thereof to which thepresent invention is applied will now be described in details withreference to the accompanying drawings.

FIG. 5 shows a first embodiment of an image signal processing apparatus1 to which the present invention is applied. The image signal processingapparatus 1 shown in FIG. 5 is built in a television receiver accordingto e.g., PAL system (Phase Alternation by Line). Image signals aftertelecine conversion or television signals (hereinafter referred to as TVsignals) are inputted to the image signal processing apparatus 1. Theimage signal processing apparatus 1 comprises, as shown in FIG. 5, afirst image memory 11, a second image memory 12, a sequence detector 13,a data selector 14, a motion vector detector 15, and an image shifter16.

The first image memory 11 is sequentially supplied with interlace imagedata of, for example, 100 fields/second which are generated byperforming double-speed conversion on images subjected to telecineconversion and have a unit-frame formed of 4 fields. The first imagememory 11 is also sequentially supplied with interlace image signals of,for example, 100 fields/second which are generated by performingdouble-speed conversion on TV signals and have a unit-frame formed of 2fields.

The first image memory 11 stores the supplied image data for every oneframe, in units of fields. That is, the image data is outputted from thefirst image memory 11 one frame after the image signals were supplied tothe first image memory 11.

The second image memory 12 has the same internal structure as the firstimage memory 11 and stores the image data supplied from the first imagememory 11 for every one frame, in units of fields. That is, the imagedata is outputted from the second image memory 12 one frame after theimage data was supplied to the second image memory 12, i.e., two framesafter the image data was supplied to the first image memory 11. Thisimage data D1 stored in the second image memory 12 is supplied to themotion vector detector 15 and image shifter 16.

The sequence detector 13 detects the image data supplied to the firstimage memory 11 and the image data outputted from the first image memory11, and compares image signal levels for every pixel, to calculate adifference value between the supplied and outputted signals. That is,the sequence detector 13 compares the image signal levels for each pixelat one single part of a screen, at cycles of frames. The sequencedetector 13 transmits the calculation result concerning the differencevalue of the image signal levels to the image shifter 16. In addition tothe above identification of each field, the sequence detector 13determines either signals after the telecine conversion or TV signals,and transmits, as distance information, the determination result to theimage shifter 16 and the like.

To the data selector 14, inputted are the image data to be supplied tothe first image memory 11 and the image data outputted from the firstimage memory 11. The data selector 14 selects one from the above twosupplied image data based on the determination result received from thesequence detector 13. That is, when the received data is determined tobe the signals after telecine conversion by the sequence detector 13,the data selector 14 selects the image data to be supplied to the firstimage memory 11. On the other hand, when the received data to isdetermined to be TV signals by the sequence detector 13, the dataselector 14 selects the image data outputted from the first image memory11. Hereinafter, the image data selected by the data selector 14 isreferred to as image data D2. The data selector 14 outputs the selectedimage data D2 to the motion vector detector 15.

Note that the data selector 14 is applicable to a connection mode inwhich one of the image data outputted from the first image memory 11 andthe image data outputted from the second image memory 12 is selected.

The motion vector detector 15 detects the image data D1 and image dataD2, and detects a motion vector based on, for example, the blockmatching method. In this block matching method, the screen is dividedinto blocks each consisting of predetermined pixels, and motion vectorsare obtained by evaluating similarity in units of blocks. The image dataD1 outputted from the second image memory 12 is a two-frame-delayedfield with respect to a reference field. The image data D2 outputtedfrom the data selector 14 is the reference field itself or theone-frame-delayed field with respect to the reference field.

That is, by detecting a motion vector between the image data D1 andimage data D2, the motion vector detector 15 can detect a motion vectorbetween the reference field and two-frame-delayed signals. In a similarfashion, it can detect a motion vector between the one-frame-delayedsignals and two-frame-delayed signals. In other words, the motion vectordetector 15 can control a field interval at which a motion vector isdetected, based on the determination result received from the sequencedetector 13.

The image shifter 16 receives the distance information including thecomparison result of image signal levels from the sequence detector 13.The image shifter 16 also receives the motion vector detected by themotion vector detector 15. Further, the image shifter 16 is suppliedwith image data D1 from the second image memory 12, and the image dataD2, from the data selector 14. The image shifter 16 shifts each pixelposition of the supplied image signals in the vector direction of thereceived motion vector within the range of the received motion vector.The internal configuration of the image shifter 16 will later bedescribed in detail.

In some cases, a double-speed field conversion circuit 3 which performsdouble-speed conversion on the field frequency of image signals may beintegrated in the image signal processing apparatus 1. The double-speedfield conversion circuit 3 is integrated to prevent screen flickerdisturbance by improving the resolution. For example, a processing suchas interpolation is performed in the PAL system, to convert image datahaving a field frequency of 50 Hz into image data having a doublefrequency which is 100 Hz.

The double-speed field conversion circuit 3 has an input terminal 31connected to the television receiver, a double-speed converter 32, and aframe memory 33, as shown in FIG. 5.

The double-speed converter 32 writes image data after the telecineconversion, which are inputted through the input terminal 31 from thetelevision receiver, or the TV signals into the frame memory 33. Thedouble-speed converter 32 reads the image data written into the framememory 33, at a speed which is twice the writing speed. As a result, forexample, the frequency of the image signals of 50 fields/secondaccording to the PAL system is converted to a double frequency, so thatimage data of 100 fields/second can be generated. The double-speedconverter 32 supplies the image signal processing apparatus 1 with theimage data subjected to the double-speed conversion.

Next, the internal configuration of the image shifter 16 will bedescribed in detail with reference to FIG. 6. The image shifter 16 iscomposed of a data processing unit 16 a and a data shift unit 16 b.

The data processing unit 16 a comprises a data buffer readout controlunit 161, a first buffer 162, a second buffer 163, a data calculationunit 164, and a flag calculation unit 165.

To the data buffer readout control unit 161, a motion vector detected inthe motion vector detector 15 is inputted. The data buffer readoutcontrol unit 161 calculates buffer control signals S11 and S12 based onthe inputted motion vector. Each of the buffer control signals S11 andS12 is formed of address signal for sequential readout of data, andenable signal. For example, in the case where each of the first andsecond buffers 162 and 163 is realized by a frame memory and the like,the data buffer readout control unit 161 calculates each of addresssignals of X- and Y-coordinates, respectively, as absolute coordinatevalues. On the other hand, in case where each of the first and secondbuffers 162 and 163 is formed of the minimum necessary memory such as aline memory, the data buffer readout control unit 161 calculates each ofaddress signals of X- and Y-coordinates as relative coordinate values.

Assuming that X- and Y-coordinates of values of an address of the buffercontrol signal S11 are (AX1, AY1) and that X- and Y-coordinates ofvalues of a supplied motion vector are (VX, VY), the address of thebuffer control signal S12 (AX2, AY2) is represented by the followingequations.AX2=AX1+VX  (1.1)AY2=AY1+VX  (1.2)

The data buffer readout control unit 161 supplies the first buffer 162with the buffer control signal S11 containing these calculated addresssignals. The data buffer readout control unit 161 supplies the secondbuffer 163 with the buffer control signal S12 containing address signalscalculated in the same way.

The first buffer 162 sequentially stores the image data D1 transmittedfrom the second image memory 12. The first buffer 162 reads out thestored image data D1 according to the supplied buffer control signalS11. More specifically, when the enable of the supplied buffer controlsignal S11 is valid, the first buffer 162 reads out the image data D1stored in the first buffer 162 according to address values contained inthe buffer control signal S11. The image data D1 thus read out ishereinafter referred to as a shift data SD1. The first buffer 162transmits the shift data SD1 to the data calculation unit 164 and theflag calculation unit 165.

The first buffer 162 may be a frame memory which stores datacorresponding to one frame, or formed of the minimum necessary memorysuch as a line memory which complies with the region that motion vectorvalues fall in. Further, the first buffer may be realized by a FIFOmemory and the like in order to sequentially read out data.

The second buffer 163 sequentially stores the image data D2 transmittedfrom the data selector 14. The second buffer 163 reads out the storedimage data D2 according to the supplied buffer control signal S12. Morespecifically, when the enable of the supplied buffer control signal S12is valid, the second buffer 163 reads out the image data D2 stored inthe second buffer 163 according to address values contained in thebuffer control signal S12. The image data D2 thus read out ishereinafter referred to as a shift data SD2. The second buffer 163transmits the shift data SD2 to the data calculation unit 164 and theflag calculation unit 165.

The second buffer 163 may be a frame memory which stores datacorresponding to one frame, or formed of the minimum necessary memorysuch as a line memory which complies with the region that motion vectorvalues fall in. In the latter case, a system in which data is randomlyread out according to the randomly supplied address values isestablished.

The data calculation unit 164 calculates move data M1 based on thesupplied shift data SD1 and shift data SD2. The data calculation unit164 sequentially supplies the data shift unit 16 b with the calculatedmove data M1.

Note that the move data M1 may be calculated by outputting the shiftdata SD1 or shift data SD2 without change, or may be calculated as anaverage value between the shift data SD1 and shift data SD2. Further,the move data M1 may be calculated by weighted-averaging the shift dataSD1 and shift data SD2 using values such as a motion vector.

The flag calculation unit 165 is supplied with the shift data SD1 andshift data SD2 and calculates a flag F1 containing error information ofthe detected motion vector. In some cases, the flag F1 is represented bya magnitude of the absolute difference value between the shift data SD1and shift data SD2. In other cases, it is calculated based on a motionvector error. Further, it may be calculated by outputting the flaginformation pertaining to the motion vector without change. The flagcalculation unit 165 supplies the data shift unit 16 b with thecalculated flag F1.

The data shift unit 16 b comprises a shift buffer readout control unit166, a shift buffer write control unit 167, and a shift buffer 168.

The shift buffer readout control unit 166 receives a motion vector fromthe motion vector detector 15, and distance information containing thedetermination result with respect to each signal from the sequencedetector 13. The shift buffer readout control unit 166 generates a shiftbuffer readout control signal RS1 based on the motion vector, distanceinformation and a built-in address counter. The shift buffer readoutcontrol signal RS1 is formed of an address signal for sequential readoutof data, and an enable signal. For example, in the case where the shiftbuffer 168 is realized by a frame memory and the like, the shift bufferreadout control unit 166 calculates address signals of X- andY-coordinates, respectively, as absolute coordinate values. On the otherhand, in the case where the shift buffer 168 is formed of the minimumnecessary memory such as a line memory, the shift buffer readout controlunit 166 calculates address signals of X- and Y-coordinates,respectively, as relative coordinate values.

Assuming that X- and Y-coordinates of values of an address denoted bythe address counter are (CX1, CY1) and that X- and Y-coordinates ofvalues of a supplied motion vector are (VX, VY), the address of theshift buffer readout control signal RS1 (SX, SY) is represented by thefollowing equations.SX=CX1+(VX×α)  (2.1)SY=CY1+(VY×α)  (2.2)where α is distance information and represented by the number which isequal to or greater than 0 and is equal to or smaller than 1. The valueof α is set to minimum in the first field, and is sequentially increasedevery time the field shifts to the next field. The value of α can beincreased linearly by ¼ in the case where the signals after telecineconversion are inputted. In this case, α shifts from 0 to ¼, 2/4, and ¾as the field shifts from the first field to the second field, the thirdfield, and the fourth field. Further, in the case where the TV signalsare inputted, the value of a can be increased linearly by ½ such that ashifts from 0 to ½ as the field shifts from the first field.

The shift buffer readout control unit 166 supplies the shift bufferwrite control unit 167 and shift buffer 168 with the generated shiftbuffer readout control signal RS1.

The shift buffer write control unit 167 is supplied with the flag F1, aflag F′ and the shift buffer readout control signal RS1 from the flagcalculation unit 165, the shift buffer 168, and the shift buffer readoutcontrol unit 166, respectively. The shift buffer 167 determines thepriority of the data to be written according to whether the flag F islarger or smaller than the flag F′. The shift buffer write control unit167 calculates a write address based on the supplied shift bufferreadout control signal RS1, and supplies the shift buffer 168 with thewrite address and the priority determined as described above, as a shiftbuffer write control signal RS2.

The shift buffer 168 is constituted by a data buffer and a flag buffer.The data buffer is a buffer for storing and providing data. The flagbuffer is a buffer for storing and providing a flag. In the data bufferand flag buffer, writing and reading operations are performed based onthe same control signals. Each of the data buffer and flag buffer may bea frame memory which stores data corresponding to one frame, or formedof the minimum necessary memory such as a line memory which complieswith the region that motion vector values fall in.

The shift buffer 168 firstly initializes the flag buffer. The flag to bewritten into the flag buffer includes mark information indicatingwhether data has been written or not. The mark information uses twomarks of “NM” and “OK”. “NM” indicates that data has not been written atthe time of initialization. Contrary, “OK” means that data has alreadybeen written.

When the enable of the shift buffer readout control signal RS1 is valid,the shift buffer 168 transmits the flag F′, with the flag F′ related tothe address, to the shift buffer write control unit 167. When the enableof the shift buffer write control signal RS2 is valid, the shift buffer168 writes the move data M1 and flag F1 into the data buffer and flagbuffer, respectively, according to the address value of the shift bufferwrite control signal RS2. After organizing the stored pixel values inserial order to create move data M2, and sequentially reading out ashift flag F2, the shift buffer 168 transmits the move data M2 and shiftflag F2 to a post processing unit 169.

The post processing unit 169 reprocesses the move data M2 based on theshift flag F2 inputted from the shift buffer 168, and outputs it as acorrection data H1 to a CRT 2.

Next, operations of the image signal processing apparatus 1 according tothe present invention will be described.

FIGS. 7A and 7B show a relationship between each of fields before andafter double-speed conversion in a double-speed field conversion circuitand pixel positions. In the figures, the abscissa axis represents timeand the ordinate axis represents the position of each pixel in thevertical direction.

The image data before the double-speed conversion are interlace image of50 fields/second according to the PAL system, and every unit-frame isformed of two fields, as shown in FIG. 7A.

On the other hand, the image data after the double-speed conversion areinterlace image of 100 fields/second. Therefore, as shown in FIG. 7B,new two fields t2′ and t1′ are generated between fields t1 and t2. Nofields are generated between fields t2 and t3 but new two fields t4′ andt3′ are generated between fields t3 and t4. Therefore, in the imagedata, every unit-frame is formed of four fields.

In some cases, those newly generated fields t1′, t2′, . . . are obtainedby using a median filter or the like, supposing that each pixel value isan intermediate value among three pixels surrounding each pixel. Thenewly generated fields t1′, t2′, . . . have the same contents as thefields t1, t2, . . . , respectively. As a result of this, everyunit-frame is formed of four fields, so that the resolution can beimproved by increasing the number of screens per unit time. Accordingly,the screen flicker disturbance can be suppressed.

FIG. 8 shows a relationship between each field and an image positionwith respect to image data subjected to the double-speed conversionafter telecine conversion in the case where an image moves in thehorizontal direction. In FIG. 8, the abscissa axis represents the imageposition in the horizontal direction, and the ordinate axis representstime. Images already subjected to the telecine conversion are, as shownin FIG. 8, supplied to the first image memory 11 at a constant timecycle, in the order of fields t1, t2′, t1′ and t2, and the images areall displayed on one equal position. As the field shifts to t3, theimage shifts in the horizontal direction (to the right side), and theimages are supplied to the first image memory 11 in the order of fieldst3, t4′, t3′ and t4.

When, for example, the field t3 is supplied to the first image memory 11(hereinafter referred to as a reference field), the field t1 whichprecedes by two frames the reference field is outputted from the secondimage memory 12 (hereinafter referred to as a two-frame-delayed field).

FIG. 9 shows a relationship between each field and an image positionwith respect to image data obtained by double converting the TV signalsin the case where an image moves in the horizontal direction. In thefields t1 and t2′ which form one single unit-frame, an equal image isdisplayed at an equal position. Similarly, in the fields t1′ and t2which form one single unit-frame, an equal image is displayed at anequal position.

The motion vector detector 15 detects a motion vector between thereference field and the two-frame-delayed field in units of pixels orblocks with respect to the signals subjected to the double-speedconversion after telecine conversion shown in FIG. 8. In the case of theexample shown in FIG. 8, the vector direction of the motion vector isthe horizontal direction (to the right side) with the two-frame-delayedfield taken as a reference, and has a vector quantity of A. Similarly,when the reference field is the field t5, the two-frame-delayed field ist3 and the vector quantity of the motion vector is B. By repeating thisprocedure, the directions and quantities of vectors can be sequentiallyobtained taking each two-frame-delayed field as a reference. The motionvector detector 15 sequentially transmits the obtained vector directionsand quantities of the motion vector to the image shifter 16.

The motion vector detector detects a motion vector between the referencefield and the one-frame-delayed field in units of pixels or blocks withrespect to the signals obtained by double-converting the TV signalsshown in FIG. 9. In the case of the example shown in FIG. 9, the vectordirection of the motion vector is the horizontal direction (to the rightside) with the one-frame-delayed field taken as a reference, and has avector quantity of C when the reference field is the field t1′.Similarly, when the reference field is the field t4′, theone-frame-delayed field is t1′ and the vector quantity of the motionvector is D. By repeating this procedure, the directions and quantitiesof motion vectors can be sequentially obtained taking eachone-frame-delayed field as a reference. The motion vector detector 74sequentially transmits the obtained vector directions and quantities ofthe motion vector to the image shifter 16.

The sequence detector 13 sequentially detects the reference fields andthose fields each of which precedes by one frame the reference fieldoutputted from the first image memory 11 (hereinafter referred to asone-frame-delayed field), and calculates difference values in pixelsignal levels at an equal pixel position.

More specifically, in the case of the telecine-converted images, thereference field t1′ and the one-frame-delayed field t1 form one singleunit-frame, so that the difference value in pixel signal levels, forexample, at a pixel position a is 0, as shown in FIG. 10. Next, thefield t2 is supplied as the reference field, and then, the field t2′becomes the one-frame-delayed field. Therefore, the difference value inpixel signal levels at a pixel position a is 0, too.

Next, the field t3 is supplied as the reference field, and then, theone-frame-delayed field is t1′. Since both of these field respectivelyform parts of different unit-frames, the difference value in pixelsignal levels at the point a is not 0 (but will be 1 hereinafter). Next,t4′ is supplied as the reference field, and then, the field t2 becomesthe one-frame-delayed field, so that the difference value in pixelsignal levels at the point a is 1, too.

Further, t3′ is supplied as the reference field, and then, theone-frame-delayed field is t3. Since both of these fields form one equalunit-frame, the difference value in pixel signal levels at the point ais 0 again. This tendency applies to reference fields suppliedthereafter. The calculated difference values of “0011” repeat in thisorder at a cycle of four fields. Hence, it is possible to specifyrelationships of each field to preceding and following fields, bydetecting the sequence for every unit of four fields.

Where this tendency is observed with respect to the one-frame-delayedfields, the difference values are “0011” in the order from the firstfield of every unit-frame. Therefore, when the difference value “0” iscalculated at first, the one-frame-delayed field detected at this timeis specified as the first field of a unit-frame (hereinafter referred toas the first field). When the difference value “0” continues, theone-frame-delayed field detected at this time is specified as the secondfield. When 1 is calculated at first to be the difference value, theone-frame-delayed field detected at this time is specified as the thirdfield. When the difference value “1” continues, the one-frame-delayedfield detected at this time is specified as the fourth field.

In the case where the TV signals are inputted, it is also necessary todetermine whether each field corresponds to the first field or thesecond field. However, since the double-speed field conversion circuit 3identifies the corresponding field at the time of double-conversion,there is no need to perform the sequence detection as described above.That is, at the time when the image signals are inputted from thedouble-speed field conversion circuit 3, each of the first and secondfields has already been specified.

FIG. 11A shows, as a one-dimensional graph, an example of the operationof the image shifter 16 in the case where the TV signals in which oneunit-frame is formed of two fields are inputted. In the operationexample of FIG. 11A, in which the TV signals are inputted, the imagedata D1 is the first field, and the image data D2 is the first field oneframe after the image data D1. In FIG. 11A, the number starting from 0is an address that indicates the pixel position, and the ordinate axisrepresents the pixel value (=pixel signal level).

In the present invention, as shown in FIG. 11B, correction data iswritten into the second field (hereinafter referred to as a write field)interposed between the image data D1 and the image data D2 which are, interms of time, different from each other so that smooth motions areobtained. That is, in the example shown in FIG. 11A, the image thatmakes the entire motion look smoothly is generated in the above writefield at the time when the image data D1 having a convex portion on theleft side thereof shifts to the image data D2 having a smooth convexportion in the middle thereof.

FIGS. 12A to 12D show a concrete operation example of the image shifter16 shown in FIG. 11A using pixel values. FIG. 12A shows the image dataD1 and the image data D2 which are to be inputted to the image shifter16. The number is an address that indicates the pixel position. Sinceeach pixel has a luminance, the pixel value is assigned for each numberin the supplied image data D1.

That is, in the operation example shown in FIG. 12A, the image data D1is represented by the pixel values of 100, 100, 200, . . . which, inthat order, correspond to the addresses indicated by the numbers 0 to11.

The image data D2 positioned after the image data D1 is represented bythe pixel values of 100, 100, 100, . . . which, in that order,correspond to the addresses indicated by the numbers 0 to 11.

The motion vector shown in FIG. 12A represents a vector quantity betweenthe image data D1 and the image data D2 with the pixel-based image dataD1 as a reference. For example, the pixel having a pixel value of 100 atthe address number 1 of the image data D1 is also at the address number1 of the image data D2 which is positioned one field behind. Hence amotion vector of 0 is obtained. For example, the pixel having a pixelvalue of 200 corresponding to address number 2 in the image data D1shifts to address number 4 in the image data D2. Hence the motion vectoris calculated as: 4−2=2. Note that arrows shown in FIG. 11A representpixel-based motion vectors.

Each of the first buffer 162 and second buffer 163 relates each pixelvalue in the image data D1 and image data D2 to address numbers, andstores it therein. For example, in the first buffer with which the imagedata D1 has been supplied, address numbers shown in FIG. 12A and thecorresponding pixel values are stored.

FIG. 12B shows processing of the data buffer readout control unit 161.The data buffer readout control unit 161 generates a buffer controlsignal S12 based on the above described equations (1.1) and (1.2). Whenthe buffer control signal S11 is assumed to be the number thatcorresponds to the address, the motion vector in the address number 1 is0, as shown in FIG. 12A. Hence the number of the buffer control signalS12 is 1, too. In the case of address number 2, in the buffer controlsignal S11, a motion vector of 2 is obtained. Hence the number of thebuffer control signal S12 is 4.

The buffer control signal S11 is supplied to the first buffer 162, fromwhich the pixel value at the number corresponding to the address in thebuffer control signal S111 is read out. The read out pixel value isrelated, as shift data SD1, to the address, and supplied to the datacalculation unit 164 and the like.

Similarly, the buffer control signal S12 is supplied to the secondbuffer 163, from which the pixel value at the number corresponding tothe address in the buffer control signal S12 is read out. The read outpixel value is related, as shift data SD2, to the address, and suppliedto the data calculation unit 164 and the like.

The bottom table of FIG. 12B shows the case where the move data M1 iscalculated as an average value between the shift data SD1 and shift dataSD2. The move data M1 is a prototype of the pixel value to be writteninto the field interposed between the image data D1 and image data D2.The flag F1 is also shown in the table, which is calculated as adifference absolute value between the shift data SD1 and shift data SD2.In the case where the difference absolute value is not 0, the pixelsignal level is considered to change between the image data D1 and imagedata D2 in the pixel corresponding to the relevant address. That is, inthe pixel corresponding to the relevant address, an error in the pixelsignal levels has occurred by the time the image data D1 shifts to theimage data D2.

FIG. 12C shows the shift buffer readout control signal RS1. In theexample shown in FIG. 12C, the value starting from 0, which is obtainedfrom the address counter (not shown) is shifted, in increments of 1, to1, 2 . . . in the plus direction. The obtained value is set as CX1, andthe distance information a is set to ½ in the equations (2.1) and (2.2).Note that the value denoted by the address counter is outputted with thevalue related to the address number in the image data D1.

In generating the shift buffer control signal RS1, when, for example,the number of the address counter is 2, the motion vector of the pixelposition corresponding to the number 2 is 2, based on FIG. 12A. Hence,the address number of the shift buffer readout control signal RS1 iscalculated, based on the equation (2.1), as: 2+2×½=3, with the resultthat 3 is obtained as the number of the shift buffer readout controlsignal RS1. Similarly, when the number of the address counter is 3, themotion vector of the pixel position corresponding to the number 3 is 2,based on FIG. 12A. Hence, the address number of the shift buffer readoutcontrol signal RS1 is calculated, with the motion vector of 2 assignedto the variable in the equation (2.1), as: 3+2×½=4, with the result that4 is obtained as the number of the shift buffer readout control signalRS1.

That is, the number of the generated shift buffer readout control signalRS1 represents the address number into which the correction data iswritten, in the write field. Thus, the flag F′ stored in the shiftbuffer 168 is read out in order to detect a write status of the addressnumber of the shift buffer control signal RS1 to the shift buffer 168.The flag F′ is returned as “NM” in the case where data has not beenwritten into the accessed address in the shift buffer 168. Contrary, theflag F′ is returned as a value of the difference absolute value to theaddress into which the data has been written.

In the example in FIG. 12C, for example, the mark representing that datahas not been written is shown for the address corresponding to thenumber from 0 to 8 of the shift buffer readout control signal RS1, themark being returned from the shift buffer 168 through the flag F′. Onthe other hand, to the address corresponding to the number 9, “NM”,which means that the data has not been written, is initially returnedand the difference absolute value is next returned as the flag F′. Thismeans that a plurality of pixel values are written into the addressnumber of the shift buffer 168, as shown in FIG. 11A in which vectormotions from the number 6 and number 9 in the image data 1 concentrateon the address number 9 in the image data 2.

The move data M1 is sequentially written into the corresponding addressnumber in the shift buffer 168 in which the flag F′ is returned as “NM”.In the case where the flag F′ has any numerical value, the flag F′ andflag F corresponding to the relevant address number are compared. Inthis case, the smaller one is made effective. As a result, the pixelvalue obtained based on the motion vector having less errors can bewritten while the image data D1 shifts to the image data D2, therebyaccurately compensating motions of the images with respect to images ofwide variations such as the images in which a plurality of motionvectors are directed to one single pixel position.

The shift buffer write control unit 162 determines the address intowhich the move data M1 is to be written based on the supplied flag F′.The shift buffer write control signal RS2 shown in FIG. 12C representsthe number corresponding to the determined address. The move data M1corresponding to the shift buffer write control signal RS2 is writteninto the shift buffer 168. In the case of number 9, for example, theflag F is 10, and flag F′ is 0. Since the F′, which is smaller than theflag F, is prioritized, the pixel value “100” based on the addressnumber 6, which has initially been written continues to be stored in theshift buffer 168.

FIG. 12C shows the result, in which the move data M2 stored in the shiftbuffer 168 is re-arranged in the order of the address number. The shiftflag F2 denotes mark information. The output of “OK” in the shift flagF2 means that the data has been written into the corresponding addressnumber. Contrary, the output of “NM” means that the data has not beenwritten into the corresponding address number. Incidentally, since datahas not been written into the address number 2, the mark “NM” isoutputted as a shift flag.

FIG. 12D shows correction data H1 obtained by subjecting the move dataM2 supplied from the shift buffer 168 to post processing. The number 2,into which data has not been written, is subjected to the postprocessing, so that data is newly written into the number 2. In the postprocessing, there might be a method of writing the data of the addressnumber 1 on the left side of the number 2 without change, calculatingthe average value of the data surrounding the number 2 or the like.

When the correction data H1 shown in FIG. 12D is written into the secondfield interposed between the image data D1 and the image data D2, entiremotion of the image becomes smooth as shown in FIG. 11A.

That is, the image signal processing apparatus 1 according to thepresent invention writes an optimum correction data capable of smoothingmotions into the field interposed between one image data and the otherimage data which are different, in terms of time, from each other, sothat discontinuity in motions of images can efficiently be eliminatedeven when the pixel value changes as the image moves, for example, inthe horizontal direction.

Further, the image signal processing apparatus 1 can efficientlyeliminate discontinuity in motions with respect to images of widevariations, in the cases where both of the image signals after telecineconversion and TV signals are inputted. As a result, the image signalprocessing apparatus 1 can be built in a television receiver to whichfilm signals and TV signals are both inputted. Further, upgrading can beeasily made by newly incorporating the image signal processing apparatus1 into the television receiver already sold, leading to an increasedversatility.

The present invention is not limited to the above embodiment. Forexample, as shown in FIG. 13, the present invention can be applied tothe image signal processing apparatus in which the flag calculation unit165 and shift buffer readout control section 166 are removed from theimage shifter 26. In the image shifter 26, the shift buffer readoutcontrol signal RS1, flag F, and flag F′ are omitted and the priority ofthe data to be written is not determined. When an overlap of the data tobe written into the address occurs in the image shifter, the data thathas already been written is overwritten by more recently calculateddata. Therefore, the control at the time of reading out the flag becomesunnecessary, so that the circuit can be simplified.

The present invention is not limited to the case of application to atelevision receiver according to the PAL system. For example, thepresent invention is applicable to a television receiver inputted withinterlace image signals of 60 fields/second (30 unit-frames/second)according to NTSC (National TV System Committee). Alternatively, thepresent invention is applicable to a television receiver according toSECAM system.

Further, the present invention is not limited to the image signalprocessing apparatus built in television receivers but may be built insignal converters connected to television receivers.

Further, the present invention is applicable to the case where the imagesignals as transferred through the Internet are displayed on the PC, andthe case where media and image format are transformed.

Still further, the present invention is realized by hardware such as acircuit, but the present invention can obviously be realized as softwareon the processor.

The present invention is not limited to the foregoing embodiment thathas been described above with reference to the drawings. Variousmodifications, substitutions, or equivalents will readily occur topersons in the art without deviating from the appended claims and thescope of subject matters thereof.

INDUSTRIAL APPLICABILITY

As has been described above in detail, in the image signal processingapparatus and the method thereof according to the present invention,signals consist of unit-frames each formed of fields with a first fieldin the lead and which have been subjected to double-speed conversion areinputted, the first field is specified on the basis of calculateddifference values in pixel signal levels, interpolation pixel data iscalculated for each detected pixel, and the interpolation pixel data iswritten into the pixel positions obtained by shifting the positions ofthe detected pixels in a direction along the motion vector such thatshift amount is gradually increased as the field shifts from thespecified first field to the following fields.

As a result of this, the image signal processing apparatus and themethod thereof according to the present invention can synergisticallyincrease image quality by smoothening motions of images whilesuppressing screen flicker disturbance with respect to images of widevariations.

1. An image signal processing apparatus comprising: sequence detectionmeans for calculating a difference value in pixel signal level between adetected pixel in a current field and a detected pixel at the sameposition in a field which comes one frame behind the current field, withrespect to the inputted image signal consist of unit-frames each formedof fields with a first field in the lead and which has been subjected todouble-speed conversion, and specifies the first field based on thedifference value; motion vector detection means for detecting a motionvector for a field which comes one frame or two frames behind thecurrent field, with respect to the detected pixel in the current field;data calculation means for calculating interpolation pixel data for thedetected pixel based on the pixel data of the detected pixel in thecurrent field and the pixel data of each pixel in the field which comesone frame or two frames behind the current field; and image controlmeans for writing the interpolation pixel data into the pixel positionobtained by shifting the position of the detected pixel in the currentfield in a direction along the motion vector, in a field subsequent tothe first field, the image control means for sequentially increasing theamount with which the position of the detected pixel is shifted everytime the field shifts from the first field to the following fieldswithin a range of a vector quantity of the detected motion vector. 2.The image signal processing apparatus according to claim 1, wherein thedata calculation means sets, as the interpolation pixel data, one of thepixel data of the detected pixel in the current field and the pixel dataobtained by shifting the pixel position in the field which comes oneframe or two frames behind the current field in the motion vectordirection by the motion vector quantity, an average value between thetwo, or a weighted-average value between the two in accordance with thevector quantity of the motion vector.
 3. The image signal processingapparatus according to claim 1, comprising flag calculation means forcalculating a flag containing error information of the detected motionvector, wherein the image control means determines the priority at thetime of writing the interpolation pixel data based on the calculatedflag.
 4. The image signal processing apparatus according to claim 3,wherein the flag calculation means calculates, as the flag, a differenceabsolute value between the pixel data of the detected pixel in thecurrent field, and the pixel data obtained by shifting the pixelposition in the field which comes one frame or two frames behind thecurrent field in the motion vector direction by the motion vectorquantity.
 5. The image signal processing apparatus according to claim 1,wherein interpolation pixel data for the pixel into which theinterpolation pixel data has not been written is determined based oninterpolation pixel data written into the pixel positions surroundingthe relevant pixel, in a field subsequent to the first field.
 6. Theimage signal processing apparatus according to claim 1, wherein theimage control means changes the shift amount in accordance with thenumber of fields each forming the unit-frame.
 7. The image signalprocessing apparatus according to claim 1, wherein image signalsgenerated by performing double-speed conversion on an image subjected totelecine conversion and which is formed of unit-frames each includingfour fields, or image signals generated by double-speed convertingtelevision signals and which is formed of unit-frames each including twofields are inputted, wherein the motion vector detection means detects amotion vector for the field which comes two frames behind the currentfield when the difference values include at least 0, and detects amotion vector for the field which comes one frame behind the currentfield when both of the difference values is not
 0. 8. The image signalprocessing apparatus according to claim 1, wherein, when the differencevalue sequentially becomes 0 in the case where the difference valuesinclude at least 0, the sequence detection means specifies the currentfield inputted earlier, as the first field.
 9. The image signalprocessing apparatus according to claim 1, wherein the image controlmeans increases the shift amount in increments of the amount obtained bydividing the vector quantity of the detected motion vector by the numberof fields each forming unit-frames every time the field shifts from thefirst field to the following fields.
 10. The image signal processingapparatus according to claim 1, wherein the motion vector detectionmeans detects the motion vector for each block formed of a predeterminednumber of pixels based on a block matching method.
 11. The image signalprocessing apparatus according to claim 1, wherein the inputted imagesignals are interlace image signals according to PAL system.
 12. Animage signal processing method, comprising the steps of: inputting animage signal consist of unit-frames each formed of fields with a firstfield in the lead and which has been subjected to double-speedconversion; calculating, with respect to the inputted image signal, adifference value in pixel signal level between a detected pixel in acurrent field and a detected pixel at the same position in a field whichcomes one frame behind the current field to specify a first field basedon the difference value; detecting a motion vector for a field whichcomes one frame or two frames behind the current field, with respect tothe detected pixel in the current field; calculating interpolation pixeldata for the detected pixel based on the pixel data of the detectedpixel in the current field and the pixel data of each pixel in the fieldwhich comes one frame or two frames behind the current field; writingthe interpolation pixel data into the pixel position obtained byshifting the position of the detected pixel in the current field in adirection along the motion vector, in a field subsequent to the firstfield; and sequentially increasing the amount with which the position ofthe detected pixel is shifted every time the field shifts from the firstfield to the following fields within a range of a vector quantity of thedetected motion vector.
 13. The image signal processing method accordingto claim 12, wherein one of the pixel data of the detected pixel in thecurrent field and the pixel data obtained by shifting the pixel positionin the field which comes one frame or two frames behind the currentfield in the motion vector direction by the motion vector quantity, anaverage value between the two, or a weighted-average value between thetwo in accordance with the vector quantity of the motion vector, is setas the interpolation pixel data.
 14. The image signal processing methodaccording to claim 12, characterized by calculating a flag containingerror information of the detected motion vector, and determining thepriority at the time of writing the interpolation pixel data based onthe calculated flag.
 15. The image signal processing method according toclaim 14, characterized by calculating, as the flag, a differenceabsolute value between the pixel data of the detected pixel in thecurrent field, and the pixel data obtained by shifting the pixelposition in the field which comes one frame or two frames behind thecurrent field in the motion vector direction by the motion vectorquantity.
 16. The image signal processing method according to claim 12,characterized by determining interpolation pixel data for the pixel intowhich the interpolation pixel data has not been written based oninterpolation pixel data written into the pixel positions surroundingthe relevant pixel, in a field subsequent to the first field.
 17. Theimage signal processing method according to claim 12, characterized bychanging the shift amount in accordance with the number of fields eachforming the unit-frame.
 18. The image signal processing method accordingto claim 12, comprising the steps of: inputting image signals generatedby performing double-speed conversion on an image subjected to telecineconversion and which is formed of unit-frames each including fourfields, or image signals generated by double-speed converting televisionsignals and which is formed of unit-frames each including two fields;detecting a motion vector for the field which comes two frames behindthe current field when the calculated difference values include at least0; and detecting a motion vector for the field which comes one framebehind the current field when both of the calculated difference valuesis not
 0. 19. The image signal processing method according to claim 12,characterized by specifying the current field inputted earlier, as thefirst field when the calculated difference value sequentially becomes 0in the case where the calculated difference values include at least 0.20. The image signal processing method according to claim 12,characterized by increasing the shift amount in increments of the amountobtained by dividing the vector quantity of the detected motion vectorby the number of fields each forming unit-frames every time the fieldshifts from the first field to the following fields.
 21. The imagesignal processing method according to claim 12, characterized bydetecting the motion vector for each block formed of a predeterminednumber of pixels based on a block matching method.
 22. The image signalprocessing method according to claim 12, wherein the inputted imagesignals are interlace image signals according to PAL system.